Multi-core in High Performance Computing

As a new emerged architecture, multi-core has been proved to be able to extract more performance from the unit chip area and a new way to valid the Moore’s Law. This article makes an basic review on multicore. About hardware, article shows that shared cache and separated cahce are two typical types of current multi-core architecture but shared cache will be the mainstream. The recent research indicates multi-core is suitable for the core-limited work load and the throughput of sequence memory is about 10% higher than the single-core system which normally has the higher clock frequency. The research has given the detailed description about communication performance about intra-CMP, inter-CMP and inter-Node for different message sizes based on MVAPICH. Some technologies for reducing memory and cache contention are also introduced. The performance of OpenMP can be improved up to 25% by using the large page size of 2MB. Using the queue-based algorithm as the barrier algorithms could improve the performance of thread libraries. Finally, using MPI between nodes and multi-thread with share memory mode in each node can exploit more SMP advantages from multi-core architecture. In order to fully utilize the potential of multi-core, more supports from multi-threaded libraries and OS are necessary. In order to utilize all advantages of multi-core, we hope gain more support from smarter OSes and libraries which will have been optimized for the architecture. More responsibilities will be lied on those vendors of libraries and OSes.